Technical Field
The present disclosure relates to a vertical bipolar transistor, and a method of fabricating thereof. The disclosure also relates to a memory cell comprising such a transistor.
Description of the Related Art
Resistive random access memory (commonly abbreviated as RRAM or ReRAM) is a type of non-volatile memory wherein data is represented by the resistance value of resistive storage elements, each comprising a resistive material between two metal electrodes. When a voltage is applied across the electrodes, conductive paths appear in the resistive material, causing its resistance value to vary between at least two states. A selection element, such as a diode or transistor, is commonly associated with each storage element for selective access thereto.
FIG. 1 shows a nonvolatile memory MEM comprising an array MA of resistive memory cells MC, M wordlines WLm (WL0 to WLM−1), N bitlines BLn (BL0 to BLN−1), a row decoder RDEC, and a column decoder CDEC. The array MA comprises M×N memory cells MC arranged in rows and columns. Each memory cell MC is coupled to the row decoder RDEC by one wordline WLm and to the column decoder CDEC by one bitline BLn. Each memory cell MC comprises a data storage element SE and a transistor T. The transistor T comprises a control terminal B coupled to a wordline WLm, a first conduction terminal E coupled to ground, and a second conduction terminal C coupled to a first electrode of the corresponding storage element SE. The storage element has a second electrode coupled to a bitline BLn.
FIG. 2 is a cross-sectional view of the memory cell MC. The transistor T is formed in a semiconductor substrate 1 of a first conductivity type (N, P). The substrate comprises a doped well 2 of a second conductivity type (P, N), a doped region 3 of the first conductivity type formed in the well, and shallow trench isolations 4 on each side of the well 2. For a transistor T of the NPN bipolar junction transistor type, the substrate 1 and the region 3 are N-doped and form conduction terminals (E, C), and the well 2 is P-doped and forms the control terminal (B) of the transistor. The substrate 1 is grounded and the well 2 further forms a wordline WLm for all memory cells formed in the well.
The storage element SE is formed above the top surface of the substrate and comprises a bottom electrode 5-1, a top electrode 5-2, and a resistive material 6 between the electrodes. The bottom electrode 5-1 is coupled by means of a supporting bottom plate 7-1 and a lower contact 8-1 to the doped region 3, and the top electrode 5-2 is coupled by means of a top plate 7-2 and a top contact 8-2 to a conductive path 9, which forms a bitline BLn. Each of the elements 5-1, 5-2, 6, 7-1, 7-2, 8-1, 8-2, 9 is formed in one or more dielectric layers, not shown for the sake of clarity.
FIG. 3 is a top view of four conventional memory cells formed at the intersections of one wordline WLm and four adjacent bitlines, BLn to BLn+3. For the sake of clarity, only the transistors T are shown for each memory cell. A wordline contact 2′ is provided to couple the well 2 to the row decoder RDEC (not shown).
Generally only a small number of memory cells can be formed within a single well, otherwise the series resistance of the well is too high. In order to reduce the resistance, the upper surface of the substrate may be silicided. Nevertheless, such a silicidation process short-circuits the well 2 and the doped regions 3, of opposite conductivity types, unless spacers 10 are previously formed above the junctions of the well 2 and regions 3. However, providing such spacers increases the size of each memory cell, determined by the width d1 and the separation d2 of the spacers 10 in one direction, and the width d3 and the separation d4 of the wells 2 in the other direction.
It may therefore be beneficial to provide a transistor of reduced size.